1. Field
One embodiment of the present invention relates to a clock supply apparatus and clock supply method applied to a processor having a plurality of clock input terminals and more particularly to a clock supply apparatus and clock supply method applied to a processor having clock input terminals whose input impedances are different from one another.
2. Description of the Related Art
Recently, game consoles and blade servers are configured by means of microprocessors of novel architectures containing a plurality of processor cores. For example, as the microprocessor, much attention is paid to a Cell Broadband Engine (Cell/B.E.). The Cell/B.E. is a multicore processor having a general processor core that is called a Power Processor Element (PPE) and eight processor cores that are each called a Synergistic Processor Element (SPE) suitable for a multimedia process. The SPE is configured to process multimedia data at high speed, linearly enhance the performance thereof with an increase in the number of cores and make it easy to perform the software control operation. The PPE schedules assignments of processes to the SPEs to efficiently operate the plural SPEs. Further, the Cell/B.E. uses XIO (registered trademark) of Rambus Co. as a memory interface and uses FlexIO as an external IO interface.
In the processor system using the Cell/B.E., communication between the Cell/B.E. and XDR (registered trademark) of a DRAM used as a main memory thereof is performed by means of an XIO-PLL clock and an operation clock for the Cell/B.E. processor core is generated from a Core-PLL clock generator. Since the impedance specifications required for the clock signals of the XIO-PLL clock and Core-PLL clock are different although they have the same frequency, the clocks are supplied to the XIO-PLL and Core-PLL of the Cell/B.E. from a plurality of independent clock generators (XCG).
Conventionally, the clock distribution technique for reducing spurious electromagnetic radiation caused by impedance mismatching between the clock transmission lines of a digital processing apparatus is known (for example, see Jpn. Pat. Appln. KOKAI Publication No. 2007-272796). With the above technique, a plurality of clock signals obtained by distributing an output of a single clock generation source are subjected to impedance conversion so as to attain matching in different transmission line impedances.
The number of clock generation sources can be reduced by using the technique of Patent Document 1. However, since the technique utilizes an emitter-follower transistor amplifier circuit for impedance conversion, the upper limit of the clock frequency tends to be limited by the response characteristic of the transistor amplifier circuit and the cost will be raised by using the transistor.
Further, the current clock generator (XCG) has four clock generation sources that generate clock signals at the same frequency with the same output impedance as a clock driver. In a processor system using the Cell/B.E., if a clock generator is provided for each impedance specification, the number of clock generation sources that are not operated is wastefully increased. Specifically, two clock generators whose impedance specifications are different are required and this increases the cost.